• 专利附录
  • 专利说明
  • 权利要求
  • 类似技术
  • 同族专利
  • 引用文献
  • 法律状态
  • 优先权
    • 专利摘要:
    The invention relates to a method for minimizing the operating voltage (Vdd) of an SRAM type memory point consisting of FDSOI-type NMOS (3) and PMOS (1) transistors, a doped subwoofer (31) extending an insulating layer (27) of the FDSOI structure, facing the transistors, a bias voltage being applied to the box, the method of adjusting the bias voltage according to the state of the memory point.
    公开号:FR3024917A1
    申请号:FR1457800
    申请日:2014-08-13
    公开日:2016-02-19
    发明作者:Christophe Lecocq；Kaya Can Akyel；Amit Chhabra；Dibya Dipti
    申请人:STMicroelectronics SA；STMicroelectronics International NV；
    IPC主号:
    专利说明:

    [0001] B13505 - 13-GR1-0652EN 1 METHOD FOR MINIMIZING THE OPERATING VOLTAGE OF A MEMORY POINT OF SRAM TYPE Domain The present application relates to a method for minimizing the operating voltage of a SRAM type memory point ("Static Random Access Memory "random access static memory" realized on FDSOI ("Fully Depleted Silicon On Insulator"). DESCRIPTION OF THE PRIOR ART FIG. 1 schematically represents a circuit of a SRAM type memory point. The memory point comprises two invertors InvO and Invl coupled in antiparallel, the output terminal OutO of the invertor InvO being connected to the input terminal ml of the invertor Inv1, and the output terminal Out1 of the invertor Inv1 being connected to the In0 input terminal of the InvO inverter. The invertor InvO comprises a P-channel MOS transistor (PMOS) 1 and an N-channel MOS transistor (NMOS) 3 connected in series between a supply potential Vdd connected to the source of the PMOS transistor 1, and a ground potential Gnd connected to the source of the NMOS transistor 3. The drains of the transistors 1 and 3 are coupled together to the output terminal OutO of the inverter InvO, the gates of the transistors 1 and 3 being coupled together to the input terminal In0 of the inverter 3024917 B13505 - 13-GR1-0652EN 2 InvO. The invertor Inv1 comprises a PMOS transistor 5 and a NMOS transistor 7 connected in series between the potential Vdd connected to the source of the PMOS transistor 5, and the ground potential Gnd connected to the source of the NMOS transistor 7. The drains of the transistors 5 and 7 are coupled together to the output terminal Out1 of the inverter Inv1, the gates of the transistors 5 and 7 being coupled together to the input terminal In1 of the inverter Inv1. The terminals In0 and Out1 are connected to a line 9 via an NMOS transfer transistor 11 and the terminals OutO and ml are connected to a line 13 via an NMOS transfer transistor 15. a value stored by the memory point can be written or read via lines 9 and 13 by applying a control potential Ctrl on the gates of the transfer transistors 11 and 15. In this memory point, the PMOS transistors of the Inverters Inv1 and Inv0 are all identical and have the same threshold voltage VtP, and the NMOS transistors of inverters Inv1 and Inv0 are all identical and have the same threshold voltage VtN. The dynamic power consumption of a circuit comprising an SRAM memory whose memory points are of the type described in relation to FIG. 1 depends notably on the square of the supply voltage of the circuit which is generally limited by the supply voltage. or Vdd operation of its SRAM memory. It would therefore be desirable to provide an SRAM memory point having an operating voltage Vdd as low as possible to reduce the consumption of a circuit comprising an SRAM memory. SUMMARY Thus, an embodiment provides a method for minimizing the operating voltage of an SRAM type memory point consisting of FDSOI-type NMOS and PMOS transistors, a doped box extending under an insulating layer of the B-type. In the structure FDSOI, opposite said transistors, a bias voltage is applied to the box, the method of adjusting the bias voltage according to the state of the memory point.
    [0002] According to one embodiment, the memory point is an element of a matrix of identical memory points, the box being common to all the memory points of the matrix. According to one embodiment, the method comprises the following successive steps making measurements representative of the threshold voltage of the NMOS transistors and the threshold voltage of the PMOS transistors; and adjusting the bias voltage of the well so that the threshold voltages of the NMOS transistors and the PMOS transistors are equal, within 10%, to target threshold voltages of the NMOS transistors and the PMOS transistors respectively. According to one embodiment, the target threshold voltages of the NMOS and PMOS transistors are equal. According to one embodiment, the method further comprises the following successive steps: measuring the operating temperature of the memory point; and slaving the bias voltage to the difference between the operating temperature and a reference temperature so as to correct the operating voltage increases resulting from a variation of said difference.
    [0003] According to one embodiment, the well is P-type doped and the bias voltage is increased as the operating temperature decreases, and the bias voltage is reduced as the operating temperature increases.
    [0004] According to one embodiment, the representative measurement of the threshold voltages is a measurement of a frequency of an oscillator consisting of a chain of inverters. In another aspect, an embodiment provides an integrated circuit chip comprising: an SRAM-type memory point consisting of FDSOI type NMOS and PMOS transistors; A doped box extending under an insulating layer of the FDSOI structure, opposite said transistors; a device for measuring the operating temperature of the memory point; and a device for controlling the polarization voltage of the box as a function of the operating temperature. According to one embodiment, the memory point is an element of a matrix of identical memory points, the box being common to all the memory points of the matrix. BRIEF DESCRIPTION OF THE DRAWINGS These and other features and advantages will be set forth in detail in the following description of particular embodiments in a non-limiting manner with reference to the accompanying figures, in which: FIG. represents a schematic circuit of a SRAM memory point; Figure 2 is a schematic sectional view showing an embodiment on FDSOI elements of the memory point of Figure 1; in accordance with the practice of representing semiconductor components, this figure is not to scale; FIG. 3 is a diagram indicating the critical operating voltage of an SRAM memory point as a function of the threshold voltages of the transistors constituting this memory point; and FIG. 4 is a schematic representation of an embodiment of an integrated circuit chip comprising an array of SRAM memory points having transistors of the type of those of FIG. 2. Detailed Description In a memory point of the type of that described in connection with FIG. 1, there is a limit value VddR of the operating voltage Vdd below which errors can occur during read operations. Similarly, there is a limit value Vdd w of the operating voltage Vdd below which errors in writing operations may occur. In order for the memory point to operate without error, the operating voltage Vdd must be chosen greater than or equal to a critical operating voltage VddcR which must be greater than the limit values VddR and Vdd.
    [0005] To reduce the consumption of a memory point, the operating voltage Vdd is chosen equal to or substantially greater than the critical operating voltage VddcR. As described in connection with Fig. 11 of N. Planes et al., "Process Architecture for Spatial and Temporal Improvement of SRAM Circuits at the 45nm node", presented in 2008 at the SSDM conference, the Making the absolute values of the VtP threshold voltages of the PMOS and VtN transistors of the NMOS transistors as close as possible leads to low critical operating voltage values VddcR. FIG. 2 partially and schematically represents an exemplary embodiment on FDSOI of transistors of a memory point of the type of that of FIG. 1. Only NMOS transistors 1 and PMOS 3 of the memory point of FIG. FIG. 2. The PMOS transistor 1 comprises, in a thin layer of silicon 21, source regions 51 and drain D1 doped P type and separated from each other by a channel formation region C1. A stack Isolated gate G1 is formed above the C1 channel forming region. The NMOS transistor 3 comprises, in the thin silicon layer 21, N-type doped D3 source and drain regions D3 and separated one from the other by a C3 channel forming region. An insulated gate stack G3 is formed over the C3 channel formation region. The silicon layer 21 is separated from a silicon substrate 25 by an insulating layer 27. The memory-point transistors are isolated from each other by isolation trenches 29 passing through the silicon layer 21 to the layer 27. Under the transistors of the memory point, the support comprises a P type doped box 31, the insulating layer 27 separating the box 31 from the silicon layer 21. Silicon regions 33 The regions 33 are isolated from the thin layer 21 by isolation trenches 29. Thus, the box 31 can be biased to a bias potential vpoi via Region-related connections 33. All the transistors of the memory point are formed above the same well 31. In an SRAM memory including a matrix of memory points, the well 31 is common to all the memory points. This type of memory point and this type of memory will be referred to hereinafter as "single-box memory point" and "single-box memory". Beyond the surface occupied by the transistors of the memory, other transistors, for example logic circuit transistors, can be formed in and on the thin film 21, these transistors can then be arranged above the pedestals. different from the common box to the transistors of the SRAM memory.
    [0006] FIG. 3 is a diagram indicating, for a single-box memory point, the value of the critical operating voltage VddcR as a function of the threshold voltages VtP and VtN of the transistors constituting this memory point. The absolute values of the voltage VtP (on the abscissa) and the voltage VtN (on the ordinate) are indicated according to an arbitrary linear scale. When designing a memory point, in order to obtain a critical operating voltage VddcR, and therefore a consumption as low as possible, the aim is to obtain equal threshold voltages VtP and VtN for the P channel transistors and In other words, it is intended to obtain an operating point on a line 35 of FIG. 3 corresponding to the case where the absolute values of the threshold voltages VtP and VtN are equal. For example, in the context of a given technology, it is desired to obtain target values VtPA and VtNA of these threshold voltages, corresponding to a point A of the diagram of FIG. which critical operating voltage is equal to VddA. The diagram of FIG. 3 can then be divided into four quadrants defined by horizontal and vertical straight lines passing through the point A. In a quadrant I, also called FF quadrant ("Fast-Fast") in the art, the values of VtP and VtN are less than VtPA and VtNA. If the VtP and VtN values become too low, the transistors will have significant leaks.
    [0007] In a quadrant II, also called SS ("Slow-Slow") quadrant in the art, the VtP and VtN values are greater than the VtPA and VtNA values. As a result, the operating voltages of the memory points of quadrant II must be greater than VddA.
    [0008] In a SF ("Slow-Fast") quadrant, the VtP values are lower than VtPA and the VtN values are greater than VtNA. As a result, the memory points may have write errors if their operating voltages are not greater than VddA.
    [0009] In a FS ("Fast-Slow") quadrant, the VtP values are greater than VtPA and the VtN values are less than VtNA. As a result, the memory points may have read errors if their operating voltages are not greater than VddA.
    [0010] Of course, in the practical realization of an SRAM containing elementary transistors, because of the manufacturing dispersions, it is impossible to place exactly under the conditions corresponding to the point A (Vtp1, VtNA, VddA). A tolerance zone 37 is defined within a curve 39 in which the corresponding memory points can still operate at a voltage substantially equal to VddA. In a direction orthogonal to that of the straight line 35, this tolerance zone corresponds substantially to memory points for which the threshold voltage VtP is equal to VtPA to 10%, and the voltage of threshold VtN is equal to VtNA to within 10%. If the fabricated circuit is such that its operating point is outside the tolerance zone 37 in a direction orthogonal to that of the line 35, it is proposed here, in the case where the SRAM is a single-box memory , to modify the polarization voltage Vpol of the box so as to bring the operating point back within the tolerance zone 37. More particularly, to bring back an operating point B situated outside the tolerance zone 37 from the quadrant SF side to a point B 'located within this zone, the polarization voltage Vpol of the box is increased, and to bring back a point C located outside the tolerance zone 37 on the side of the FS quadrant to a point C 'located within this zone, the bias voltage Vpol of the box is reduced. The fact that an operating point is outside the tolerance zone 37 can result from many reasons.
    [0011] A first reason is, as previously indicated, that inevitably there are manufacturing dispersions. In this case, the correction of the polarization voltage is determined following initial tests in which the VtP and VtN values are measured directly or indirectly to determine in which quadrant, more particularly the quadrant SF or the quadrant FS, find the operating point. Following these initial tests, the bias voltage Vpol is modified as previously indicated. The values of the threshold voltages VtP and VtN are, for example, deduced from the measurement of the frequency of an oscillator consisting of a chain of inverters whose constituent transistors are identical to those of the memory points, and are realized at above the same box 31 common to the transistors of these memory points.
    [0012] A second reason is that there are parameter variations during the operation of a memory point, for example, temperature variations inevitably occur. In the latter case, in order to perform the corresponding correction, provision is made to insert a temperature sensor into the integrated circuit chip containing the SRAM memory and the bias voltage Vpol will be temperature-controlled. More particularly, for an operating point C 'located in the tolerance zone 37 and in the quadrant FS, an increase in temperature causes the operating point to move towards the point C in the quadrant FS. The bias voltage Vpol is then reduced to bring the operating point back to the tolerance zone 37. Conversely, for an operating point B 'located in the tolerance zone 37 and in the quadrant SF, a temperature decrease results in that the operating point moves to the operating point B in the quadrant SF. The bias voltage Vpol is then increased to bring the operating point back to the tolerance zone 37.
    [0013] FIG. 4 shows a schematic example of an integrated circuit chip 50 comprising a single-box SRAM type memory 52. According to one embodiment, the chip 50 further comprises a temperature sensor 54 and a device 52 for controlling the bias voltage Vpol of the single box. The servocontrol device 56 is powered by a voltage Vcc and supplies the bias voltage Vpol to the box 31 of the SRAM memory 52. The bias voltage Vpol is determined by the servocontrol device 56, for example on the basis of the T value of the operating temperature of the single-box memory, T being provided by the temperature sensor 54. Particular embodiments have been described. Various variations and modifications will be apparent to those skilled in the art. In particular, although there has been described a single-box SRAM memory point in which the transfer transistors 10 and 15 are N-channel MOS transistors, the present disclosure applies also in the case where these transistors are P-channel MOS transistors. Although an embodiment of a method for optimizing the consumption of an SRAM formed above a box 31 has been described. P type doped, which has been previously described applies to an N-type well 31. In addition, the method of minimizing the consumption of an SRAM memory point has been previously described for VtNA target threshold voltages. and VtPA equal. This method also applies to target threshold voltages VtNA and VtPA not being equal. The method of minimizing the consumption of an SRAM memory point has been described for a six-transistor SRAM memory point. This method can also be applied to SRAM memory points comprising a different number of transistors.
    权利要求:
    Claims (9)
    [0001]
    REVENDICATIONS1. A method for minimizing the operating voltage (Vdd) of an SRAM type memory point consisting of FDSOI type NMOS transistors (3, 7, 11, 15) and PMOS (1, 5), a doped box (31) extending under an insulating layer (27) of the FDSOI structure, facing said transistors, a bias voltage (Vpol) being applied to the box, the method of adjusting the bias voltage (Vpol) according to the state of the memory point.
    [0002]
    The method of claim 1, wherein the memory point is an element of an array of identical memory points, the well (31) being common to all memory points of the array.
    [0003]
    3. The method of claim 1 or 2, comprising the following steps: making measurements representative of the threshold voltage (VtN) of the NMOS transistors (3, 7, 11, 15) and the threshold voltage (VtP) PMOS transistors (1, 5); and adjusting the bias voltage (Vpol) of the well (31) so that the threshold voltages of the NMOS transistors and the PMOS transistors are equal, within 10%, to target threshold voltages of the NMOS transistors and the PMOS transistors respectively.
    [0004]
    The method of claim 3, wherein the target threshold voltages of the NMOS and PMOS transistors are equal.
    [0005]
    5. Method according to any one of claims 1 to 4, further comprising the following successive steps: measuring the operating temperature (T) of the memory point; and servocating the bias voltage (Vpol) to the difference between the operating temperature and a reference temperature so as to correct the operating voltage increases (Vdd) resulting from a variation of said difference. 3024917 B13505 - 13-GR1-0652EN 12
    [0006]
    The method of claim 5, wherein the well is P-type doped and the bias voltage (vpol) is increased as the operating temperature decreases, and the bias voltage is reduced as the operating temperature increases.
    [0007]
    7. Method according to any one of claims 3 to 6, wherein the representative measurement of the threshold voltages (VtN, VtP) is a measurement of a frequency of an oscillator consisting of a chain of inverters.
    [0008]
    An integrated circuit chip comprising: a memory point of the NMOS type (3, 7, 11, 15) and PMOS (1, 3) an insulated doped box (31) (27) of the transistor structure; an SRAM measuring device consisting of FDSOI type transistors; extending under an FDSOI layer, opposite said (54) operating temperature (T) of the memory point; and a servo device (56) for the bias voltage (vpol) of the box as a function of the operating temperature.
    [0009]
    The integrated circuit chip of claim 8, wherein the memory point is an element of an array of identical memory points (52), the well (31) being common to all memory points of the array.
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    同族专利:
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    引用文献:
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    法律状态:
    2015-07-27| PLFP| Fee payment|Year of fee payment: 2 |
    2016-02-19| PLSC| Search report ready|Effective date: 20160219 |
    2016-07-20| PLFP| Fee payment|Year of fee payment: 3 |
    2017-07-20| PLFP| Fee payment|Year of fee payment: 4 |
    2018-07-20| PLFP| Fee payment|Year of fee payment: 5 |
    2019-07-22| PLFP| Fee payment|Year of fee payment: 6 |
    2020-07-21| PLFP| Fee payment|Year of fee payment: 7 |
    优先权:
    申请号 | 申请日 | 专利标题
    FR1457800A|FR3024917B1|2014-08-13|2014-08-13|METHOD FOR MINIMIZING THE OPERATING VOLTAGE OF A MEMORY POINT OF SRAM TYPE|FR1457800A| FR3024917B1|2014-08-13|2014-08-13|METHOD FOR MINIMIZING THE OPERATING VOLTAGE OF A MEMORY POINT OF SRAM TYPE|
    US14/813,278| US9390786B2|2014-08-13|2015-07-30|Method of minimizing the operating voltage of an SRAM cell|
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